This invention relates generally to techniques of integrated electronic circuit design, and particularly to a process of modifying or revising an existing integrated circuit layout.
The steps required in order to design masks used to form the various layers on an integrated electronic circuit are many. The first major step, after defining what the circuit is to do, is to prepare a schematic diagram showing all of the circuit elements and their interconnections. The function of the circuit is then tested by computer simulation of expected operating conditions. In the course of such testing, a net list of the circuit schematic is developed. A net list describes the schematic diagram by assigning a unique number to each digital logic gate or other circuit component, and a separate identification for each terminal of the component. The schematic diagram is then expressed as a net list of interconnections among the identified gate terminals and input/output points of the circuit.
The schematic circuit is then converted to a circuit layout by designing a number of masks which, when used to make an integrated circuit chip, implements the circuit initially designed as a schematic diagram. This is accomplished by a layout designer with the help of sophisticated computer programs. When the designer has completed the layout work, a net list is extracted from the resulting layout computer data by a commercially available net list extraction computer software program. This net list is then compared with the original schematic net list as a check on whether the layout was done properly. This comparison is accomplished by a commercially available net list comparison computer software program which gives an output that identifies the differences in the net list. The layout designer can then use a layout editing computer software program to modify the layout database in order to eliminate any differences. The process identifies mask layout errors without first having to make an actual integrated circuit.
Recently, integrated circuit manufacturers have found it necessary to modify the layout of a circuit product wherein the schematic diagram is unavailable. This can occur due to some error in maintaining records but more often occurs when rights to the circuit design are acquired from another and the layout database is all that is provided about the product. Modifications of the layout, under these circumstances, are done very carefully since there is no schematic diagram with which to compare the resulting modified layout in order to confirm that the circuit schematic being implemented has not changed. This is very time consuming and any errors that might occur when the layout is modified will not be identified until the circuit is actually formed, an expensive process. Some have manually reconstructed the schematic diagram from the layout database in order to have something with which the modified layout can be verified but this also is a very labor intensive and expensive process. These disadvantages have limited the number and complexity of layout editing that is performed when the schematic is not available.
Therefore, it is a primary object of the present invention to provide an improved technique for determining whether editing of a layout database has inadvertently caused the underlying circuit to be modified.
It is another object of the present invention to provide such a technique that is simple, less time consuming and less costly than the aforementioned alternative layout verification techniques.